In commonly owned U.S. patent application Ser. No. 839,883, filed 6 Oct. 1977 by Mario Bambara et al, now U.S. Pat. No. 4,160,289, there has been described a data processor dialoguing with a multiplicity of peripheral units with which the processor is able to exchange data in the presence of input/output instructions read out from a program memory. The macroinstructions stored in that memory (which also include transfer and branching instructions besides the aforementioned input/output instructions) are decoded in a control unit which establishes a subroutine on the basis of bit combinations of a current instruction, entered by the program memory in an associated register, and bit combinations of a forthcoming instruction present in the output of the memory but not yet loaded into the register. Each subroutine involves the readout of a number of microinstructions stored in another memory within the control unit itself.
Certain peripheral units (e.g. teletypewriters), when ready to transmit data to the processor, require an interruption of the program since their operating speed is slower than that of the processor. In the system of the prior Bambara et al application (U.S. Pat. No. 4,160,289) referred to, such program interruptions rank lower than an execution command emitted at the end of a microroutine as determined by a first priority coder within the control unit. A second priority coder in the control unit establishes an order of precedence among different peripheral units which may call for an interruption of the processor program. A subunit within the control unit prevents the occurrence of program interruptions at the conclusion of two immediately consecutive microroutines, thus requiring the extraction of at least one new macroinstruction from the corresponding memory between successive interruptions. A single peripheral unit, therefore, can occupy the processor for a limited time only.